Many complex integrated circuits make use of lateral double diffused MOSFET transistors capable of supporting relatively high voltages (40-60V) (LDMOS: lateral double diffused metal oxide semiconductor) both of N-channel and P-channel type, and P channel vertical MOSFET transistors, again for relatively high voltages. By way of example, in FIG. 1 of the attached drawings is shown a schematic partial section of an N-channel LDMOS transistor structure according to the prior art. This transistor is formed on an epitaxial layer of N-type 1, formed, in turn, on a P-type monocrystalline silicon substrate, not shown, and has an interdigitate geometry, that is to say, it is composed of copenetrating modular functional elements. In the drawing, there are shown two source elements and one drain element, with their associated gate electrodes.
More particularly, the structure of FIG. 1 comprises insulating elements 2 in the form of lands of relatively thick silicon dioxide, for example 1 .mu.m, obtained by a known insulating technique by selective oxidation of the silicon with a silicon nitride mask. The insulating elements 2 separate silicon surfaces between them, the so-called active areas. In alternate active areas are formed P-type regions 3, the so-called "body" regions of the transistor, within which are formed respective source regions 4 of strongly doped N-type (N+).
The source regions 4 are traversed by strongly doped P-type regions 5 (P+) which serve to contact the body regions 3.
Suitable metal strips 6 in ohmic contact with the regions 4 and 5 are joined together to form the source terminal S of the transistor.
In the active areas between each two source elements, the epitaxial layer 1 is locally doped with N-type doping material in such a way as to form strongly doped N-type regions 7 (N+) which, together with the zones of the epitaxial layer 1 adjacent to it, constitute the elementary drain regions.
Metal strips 61 are also formed on these regions, only one of which is visible in FIG. 1, in ohmic contact and joined together to form the drain terminal D of the transistor.
The edge zones of the body region 3, which constitute the channel zones of the transistor, are overlain by relatively thin layers (for example 0.005 .mu.m) of silicon dioxide 8. Over these layers and over edge portions of the insulating elements of field oxide 2 are formed layers of electroconductive material, for example, doped polycrystaline silicon 9, which are joined together to form the gate electrode G of the transistor.
The strips 9 also fulfill the function of field electrodes for the drain junctions, that is to say, for the junctions between the body regions 3 and the drain regions 7, 1. In operation of the transistor, these junctions are polarized in the inverse sense and the field electrode is normally at a potential, with respect to that of the drain, which has the effect of reducing the electric field of the junction in proximity to the silicon surface and thus of increasing the maximum breakdown voltage between source and drain of the transistor.
In order to reduce both the area occupied by the transistor and the series resistance of the transistor in direct conduction it is sought to reduce as much as possible the width of the insulating elements of field oxide 2. The minimum width of these elements is, however, set by various fabrication requirements. In particular, the minimum distance between the edge of the strip 9 and the extremity of the field oxide 2 closest to the drain region 7, indicated d1 in FIG. 1, is determined by the maximum possible alignment error with the photolithographic technique utilized and the minimum distance between the same edge and the other extremity of the field oxide 2 indicated d2 is determined by the maximum breakdown voltage which it is desired to obtain.